1. Field of the Invention
The present invention relates to a semiconductor device having a thin film capacitor and a method for fabricating the same.
2. Description of the Related Art
Heretofore, in a general purpose DRAM, Ta2O5 having a high dielectric constant has been considered as a capacitor dielectric film in a memory cell. In this case, it is an ordinary practice that a lower electrode of a capacitor is formed of a polysilicon layer which can be formed to have a concavo-convex surface (for example, so called HSG (hemi-spherical grain) structure) in order to increase a capacitance per a unitary area. In order to form this polysilicon layer, a high temperature process on the order of 700 to 900 degrees Celsius is required.
On the other hand, in a logic mixed DRAM in which a logic section and a memory section are formed on the same chip, gate electrodes and source/drain diffused regions in the logic section are required to be provided with a cobalt (Co) silicide for a speedup of transistors.
The cobalt silicide layer can realize a low resistance, however, if the temperature is elevated, aggregation occurs in the cobalt silicide layer so that the resistance value of the gate electrodes and the diffused layers increases. Therefore, in a process after formation of the cobalt silicide layer, the process temperature cannot be elevated. For example, in the generation of the gate length of 0.15 micron, about 600 degrees Celsius is an upper limit.
Accordingly, if Ta2O5 is used to form a capacitor dielectric film in the memory section of the logic mixed DRAM and if a polysilicon layer is used to form a lower capacitor electrode, a high temperature process is required to form the polysilicon layer, with the result that the transistors in the logic section become deteriorated through the high temperature process. Therefore, in the generation of the gate length of 0.15 micron and in succeeding generations, it is not possible to use the polysilicon for the lower capacitor electrode. Under this situation, there is a demand for constitute the electrode of the capacitor with a metal or a metal nitride, for example, TiN (titanium nitride), W (tungsten) or Ru (ruthenium), which can be formed at a low temperature of not greater than 500 degrees Celsius where no aggregation occurs in the cobalt silicide.
Now, explanation will be made on a conventional method for forming a thin film capacitor, using a metal or a metal nitride for the lower capacitor electrode and also using Ta2O5 for the capacitor dielectric film.
A lower electrode of TiN, W or Ru is formed by a CVD (chemical vapor deposition) or a PVD (physical vapor deposition), and then, a Ta2O5 capacitor dielectric film is formed by a thermal CVD process. Thereafter, in order to reduce a leakage current in the Ta2O5 capacitor, a post anneal is carried out with a RTO (rapid thermal oxidation) or a UV-O3 oxidation at a temperature of not less than 500 degrees Celsius. Furthermore, an upper electrode of TiN or another is formed by the CVD process or the PVD process, and then, a patterning is carried out to have a desired shape. Thus, the thin film capacitor of a MIM structure having the capacitor dielectric film formed of Ta2O5 is obtained.
FIG. 14A is a diagrammatic section view of a capacitor formed of a capacitor dielectric film formed of Ta2O5 and upper and lower capacitor electrodes of TiN. FIG. 14B is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) and a leakage current in the structure shown in FIG. 14A. FIG. 14B shows the leakage current at temperatures of 25 degrees Celsius, 85 degrees Celsius and 125 degrees Celsius. It would be seen from this figure that the leakage current remarkably increases when the temperature becomes not less than 85 degrees Celsius which is a device operation guarantee temperature.
Furthermore, in a LSI chip, it is considered to form a high dielectric constant thin film capacitor above interconnections in the LSI, so as to use it as a decoupling capacitor. The decoupling capacitor is provided to compensate for a voltage drop which is caused for a parasite inductance existing between a power supply and interconnections of the LSI.
Referring to FIG. 15, a conventional decoupling capacitor is shown. In the prior art, as shown in FIG. 15, a number of laminated ceramic capacitors 93 are located around a LSI chip 92 mounted on a printed circuit substrate 91, so that those capacitors function as the decoupling capacitor. However, a resonance frequency of the laminated ceramic capacitor is on the order of about 80 MHz, and therefore, when the LSI is speeded up to several hundred MHz to several GHz, a satisfactory electric charge compensation cannot be carried out, so that it does not function as the decoupling capacitor.
FIG. 16 illustrates a thin film capacitor used as the decoupling capacitor. A high dielectric constant thin film capacitor is formed over an uppermost interconnection layer in a semiconductor device, so as to constitute an on-chip decoupling capacitor.
As shown in FIG. 16, over a wiring conductor or interconnection (ground line) 94 and a wiring conductor or interconnection (power supply line) 95, a lower electrode film, a capacitor dielectric film and an upper electrode film are deposited in the named order by a CVD process, and then, patterned into a desired shape, so as to form a thin film capacitor composed of a lower electrode 96, a capacitor dielectric film 97 and an upper electrode 98. This thin film capacitor constitutes a decoupling capacitor 99. Here, the lower electrode 96 and the upper electrode 98 are formed of TiN, and the capacitor dielectric film 97 is formed of Ta2O5. In addition, in order to reduce a leakage current, after the capacitor dielectric film 97 of Ta2O5 is formed, a UV-O3 anneal is carried out at a temperature of 500 degrees Celsius.
In the case of forming a high dielectric constant thin film capacitor over the uppermost interconnection layer in the semiconductor device to use it as the decoupling capacitor, the demand of a low inductance and a large capacitance is satisfied with a one-chip feature and use of a high dielectric constant capacitor,
As mentioned above, in the conventional thin film capacitor having the lower electrode formed of TiN, W or Ru and the capacitor dielectric film of Ta2O5, it is necessary to carry out the post-anneal in an oxidizing atmosphere since the leakage current is large in a condition just after the formation of Ta2O5. However, because of this post anneal, the lower electrode layer is oxidized so that a low dielectric constant film is formed. As a result, even if the thickness of the Ta2O5 film is reduced, a large capacitance cannot be obtained.
In addition, because of the oxidation occurring in the post anneal, a concavo-convex or a peeling occurs in the lower electrode layer, with the result that the yield of production lowers.
Furthermore, as shown in FIG. 14B, although the leakage current is no problem at a room temperature of 25 degrees Celsius, if the temperature is elevated to 85 degrees Celsius and further to 125 degrees Celsius, the leakage current increases, so that a sufficient capacitance characteristics cannot be ensured at a device operation guarantee temperature.
On the other hand, in the case that a high dielectric constant thin film capacitor is formed over the uppermost interconnection layer in the semiconductor device and is used as the decoupling capacitor, the demand of a low inductance and a large capacitance is satisfied with a one-chip feature and use of a high dielectric constant capacitor, but the present method for forming the thin film capacitor has a problem.
It has been proposed to use Ta2O5, SrTiO3 and (Ba, Sr)TiO3 formed by the PVD process or the CVD process, for the capacitor dielectric film of the above mentioned thin film capacitor. However, in order to obtain a capacitor dielectric film of an excellent quality having a large capacitance in the conventional method utilizing the PVD or CVD process, a high temperature of not less than 400 degrees Celsius is required. In addition, in order to reduce the leakage current, it is also necessary to carry out the post anneal in the oxidizing atmosphere at the temperature of not less than 450 degrees Celsius.
Furthermore, recently, a copper wiring conductor is used for interconnection. Therefore, in the case that a capacitor is formed over the uppermost interconnection layer, if the temperature is elevated to not less than 450 degrees Celsius, the interconnection layer is oxidized, with the result that the characteristics deteriorate and the yield of production lowers.
In other words, the conventional method for forming the thin film capacitor can realize a large-capacitance, low-inductance, one-chip decoupling capacitor which meet with the speedup of the LSI.